1. Field of the Invention
The present invention relates to a method of designing a semiconductor device.
2. Description of Related Art
In manufacturing processes of a semiconductor, many processes using plasma are included. The processes such as reactive ion etching, plasma CVD, a film formation and the like are performed with a wafer placed in the plasma.
However, since electric charges exist in the plasma, in these manufacturing processes, the electric charges flow into a conductive portion exposed to a wafer surface and a device is electrically charged. In the case where this conductive portion is connected to a gate electrode (hereinafter referred to as a “gate”), an electric current flows from the gate to a substrate. At that time, a gate insulating film is damaged.
For example, as shown in FIG. 1, a wiring 6 is connected onto a gate 1 of a transistor. The wiring 6 includes a via 4 provided on the gate 1 and a wiring layer 5 provided on the via 4. In the case where this wiring 6 is connected to the gate 1, the electric current flows from the gate 1 to a substrate (not shown). At that time, a gate insulating film below the gate 1 is damaged.
In general, such damage is referred to as “antenna damage”.
Therefore, a rule is provided in order to prevent the antenna damage, which is referred to as an “antenna rule”. The antenna rule is calculated with a ratio of a gate area in a layout shape to an exposed area of the wiring connected thereto. A violation of the antenna reference when the wiring is carried out is referred to as “antenna violation”. In the case where an antenna violation occurs, correction (rearrangement) of the wiring is performed in order to avoid the antenna violation.
For example, in the technique described in Japanese Patent Publication No. JP2007-293822A, the correction of the wiring is performed referring to the gate area.
I have now discovered the following facts.
It is known a method for manufacturing a semiconductor device by configuring a circuit including the transistor mentioned above to be a cell and arranging a plurality of the cells on a chip. For example, as shown in FIG. 2, a cell 7 includes diffusion layers 2 and a poly-silicon layer 3. The gate 1 mentioned above is provided on a portion where the gate insulating film and the poly-silicon layer 3 are overlapped on the substrate surface between the diffusion layers 2.
In recent microprocess, a size of the gate 1 becomes smaller. Even if the same cell is used, a shape of the gate 1 delicately changes depending on a location in which the cell is placed. A reason thereof includes a change in the shape of the gate 1 depending on a peripheral shape in lithography and etching processes.
For example, as shown in FIG. 3, in the case where a cell 7′ and a cell 7″ are arranged on the chip as the cells 7, the gate 1 of the cell 7′ may become larger and the gate 1 of the cell 7″ may become smaller depending on the shapes of the peripheral patterns in the same layer as the gate 1.
Since the variation of the shape due to these arranged locations is not considered in checking the antenna reference, it is determined whether or not there is an error based on the shape and area of the layout, and then the correction of all wirings connected to the gates associated with the error is performed. As a result, TAT (Turn Around Time; time required for a loop of a series of steps for developing and manufacturing) is extremely consumed.